[RISCV] Implement MC support for Zvfofp8min extension #157014
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@llvm/pr-subscribers-clang-driver @llvm/pr-subscribers-backend-risc-v Author: Jim Lin (tclin914) ChangesThis patch adds MC support for Zvfofp8min Full diff: https://github.com/llvm/llvm-project/pull/157014.diff 15 Files Affected:
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 3fa5ef9afd143..b8e7724a9602a 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -216,6 +216,7 @@
// CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and Store-Release Instructions)
// CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)
// CHECK-NEXT: zvfbfa 0.1 'Zvfbfa' (Additional BF16 vector compute support)
+// CHECK-NEXT: zvfofp8min 0.21 'Zvfofp8min' (Vector OFP8 Converts)
// CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)
// CHECK-NEXT: zvqdotq 0.0 'Zvqdotq' (Vector quad widening 4D Dot Product)
// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 204c9851e680c..962375de398dc 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -178,6 +178,7 @@
// CHECK-NOT: __riscv_ztso {{.*$}}
// CHECK-NOT: __riscv_zvbc32e {{.*$}}
// CHECK-NOT: __riscv_zvfbfa {{.*$}}
+// CHECK-NOT: __riscv_zvfofp8min {{.*$}}
// CHECK-NOT: __riscv_zvfbfmin {{.*$}}
// CHECK-NOT: __riscv_zvfbfwma {{.*$}}
// CHECK-NOT: __riscv_zvkgs {{.*$}}
@@ -1560,6 +1561,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFA-EXT %s
// CHECK-ZVFBFA-EXT: __riscv_zvfbfa 1000{{$}}
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32ifzvfofp8min0p21 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFOFP8MIN-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64ifzvfofp8min0p21 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFOFP8MIN-EXT %s
+// CHECK-ZVFOFP8MIN-EXT: __riscv_zvfofp8min 21000{{$}}
+
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_zve32x_zvbc32e0p7 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVBC32E-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index d6c7b46485ccf..5d2824d797182 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -236,6 +236,7 @@ on support follow.
``Zvfbfwma`` Supported
``Zvfh`` Supported
``Zvfhmin`` Supported
+ ``Zvfofp8min`` Assembly Support
``Zvkb`` Supported
``Zvkg`` Supported (`See note <#riscv-vector-crypto-note>`__)
``Zvkn`` Supported (`See note <#riscv-vector-crypto-note>`__)
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index ff92d7390ecfd..84d68691b33de 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -120,6 +120,7 @@ Changes to the RISC-V Backend
using `$x` with an architecture string suffix is not yet supported.
* Ssctr and Smctr extensions are no longer experimental.
* Add support for Zvfbfa (Additional BF16 vector compute support)
+* Add support for Zvfofp8min (OFP8 conversion extension)
Changes to the WebAssembly Backend
----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index fa8272b239d99..ca94fa7a84d35 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -689,9 +689,6 @@ def HasStdExtZvfbfa : Predicate<"Subtarget->hasStdExtZvfbfa()">,
def FeatureStdExtZvfbfmin
: RISCVExtension<1, 0, "Vector BF16 Converts", [FeatureStdExtZve32f]>;
-def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,
- AssemblerPredicate<(all_of FeatureStdExtZvfbfmin),
- "'Zvfbfmin' (Vector BF16 Converts)">;
def FeatureStdExtZvfbfwma
: RISCVExtension<1, 0, "Vector BF16 widening mul-add",
@@ -717,6 +714,22 @@ def HasStdExtZfhOrZvfh
"'Zfh' (Half-Precision Floating-Point) or "
"'Zvfh' (Vector Half-Precision Floating-Point)">;
+def FeatureStdExtZvfofp8min
+ : RISCVExperimentalExtension<0, 21,
+ "Vector OFP8 Converts", [FeatureStdExtZve32f]>;
+def HasStdExtZvfofp8min
+ : Predicate<"Subtarget->hasStdExtZvfofp8min()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvfofp8min),
+ "'Zvfofp8min' (Vector OFP8 Converts)">;
+
+def HasStdExtZvfbfminOrZvfofp8min
+ : Predicate<"Subtarget->hasStdExtZvfbfmin() ||"
+ "Subtarget->hasStdExtZvfofp8min()">,
+ AssemblerPredicate<(any_of FeatureStdExtZvfbfmin,
+ FeatureStdExtZvfofp8min),
+ "'Zvfbfmin' (Vector BF16 Converts) or "
+ "'Zvfofp8min' (Vector OFP8 Converts)">;
+
// Vector Cryptography and Bitmanip Extensions
def FeatureStdExtZvkb
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 23f5a848137c4..a3736620ccaee 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2349,6 +2349,7 @@ include "RISCVInstrInfoZk.td"
include "RISCVInstrInfoV.td"
include "RISCVInstrInfoZvk.td"
include "RISCVInstrInfoZvqdotq.td"
+include "RISCVInstrInfoZvfofp8min.td"
// Packed SIMD
include "RISCVInstrInfoP.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
index cbeec9ba75f16..8f8fcb5d32feb 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
@@ -17,7 +17,8 @@
// Instructions
//===----------------------------------------------------------------------===//
-let Predicates = [HasStdExtZvfbfmin], Constraints = "@earlyclobber $vd",
+let Predicates = [HasStdExtZvfbfminOrZvfofp8min],
+ Constraints = "@earlyclobber $vd",
mayRaiseFPException = true in {
let RVVConstraint = WidenCvt, DestEEW = EEWSEWx2 in
defm VFWCVTBF16_F_F_V : VWCVTF_FV_VS2<"vfwcvtbf16.f.f.v", 0b010010, 0b01101>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfofp8min.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfofp8min.td
new file mode 100644
index 0000000000000..86cab697cbf55
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfofp8min.td
@@ -0,0 +1,26 @@
+//===- RISCVInstrInfoZvfofp8min.td - 'Zvfofp8min' ----------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'Zvfofp8min'
+// extension, providing vector conversion instructions for OFP8.
+// This version is still experimental as the 'Zvfofp8min' extension hasn't been
+// ratified yet.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZvfofp8min], Constraints = "@earlyclobber $vd",
+ mayRaiseFPException = true, Uses = [FRM, VL, VTYPE] in {
+ defm VFNCVTBF16_SAT_F_F_W
+ : VNCVTF_FV_VS2<"vfncvtbf16.sat.f.f.w", 0b010010, 0b11111>;
+ defm VFNCVT_F_F_Q : VNCVTF_FV_VS2<"vfncvt.f.f.q", 0b010010, 0b11001>;
+ defm VFNCVT_SAT_F_F_Q : VNCVTF_FV_VS2<"vfncvt.sat.f.f.q", 0b010010, 0b11011>;
+}
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index b53a1b95431aa..acf8e4cf7c6d2 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -153,7 +153,7 @@ namespace RISCVVType {
//
// Bits | Name | Description
// -----+------------+------------------------------------------------
-// 8 | altfmt | Alternative format for bf16
+// 8 | altfmt | Alternative format for bf16/ofp8
// 7 | vma | Vector mask agnostic
// 6 | vta | Vector tail agnostic
// 5:3 | vsew[2:0] | Standard element width (SEW) setting
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 909bb91b1e291..dc51291086b99 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -162,6 +162,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfa %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFA %s
; RUN: llc -mtriple=riscv32 -mattr=+zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfofp8min %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFOFP8MIN %s
; RUN: llc -mtriple=riscv32 -mattr=+zacas %s -o - | FileCheck --check-prefix=RV32ZACAS %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zalasr %s -o - | FileCheck --check-prefix=RV32ZALASR %s
; RUN: llc -mtriple=riscv32 -mattr=+zama16b %s -o - | FileCheck --check-prefixes=CHECK,RV32ZAMA16B %s
@@ -327,6 +328,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFA %s
; RUN: llc -mtriple=riscv64 -mattr=+zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfofp8min %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFOFP8MIN %s
; RUN: llc -mtriple=riscv64 -mattr=+zacas %s -o - | FileCheck --check-prefix=RV64ZACAS %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zalasr %s -o - | FileCheck --check-prefix=RV64ZALASR %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV64ZICFILP %s
@@ -522,6 +524,7 @@
; RV32ZVFBFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfa0p1_zvl32b1p0"
; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
+; RV32ZVFOFP8MIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p21_zvl32b1p0"
; RV32ZACAS: .attribute 5, "rv32i2p1_zaamo1p0_zacas1p0"
; RV32ZALASR: .attribute 5, "rv32i2p1_zalasr0p1"
; RV32ZAMA16B: .attribute 5, "rv32i2p1_zama16b1p0"
@@ -685,6 +688,7 @@
; RV64ZVFBFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfa0p1_zvl32b1p0"
; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
+; RV64ZVFOFP8MIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p21_zvl32b1p0"
; RV64ZACAS: .attribute 5, "rv64i2p1_zaamo1p0_zacas1p0"
; RV64ZALASR: .attribute 5, "rv64i2p1_zalasr0p1"
; RV64ZALASRA: .attribute 5, "rv64i2p1_a2p1_zaamo1p0_zalasr0p1_zalrsc1p0"
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index d13a5a4e2b9be..35673797fc6a6 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -56,6 +56,7 @@
; CHECK-NEXT: experimental-zicfiss - 'Zicfiss' (Shadow stack).
; CHECK-NEXT: experimental-zvbc32e - 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements).
; CHECK-NEXT: experimental-zvfbfa - 'Zvfbfa' (Additional BF16 vector compute support).
+; CHECK-NEXT: experimental-zvfofp8min - 'Zvfofp8min' (Vector OFP8 Converts).
; CHECK-NEXT: experimental-zvkgs - 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography).
; CHECK-NEXT: experimental-zvqdotq - 'Zvqdotq' (Vector quad widening 4D Dot Product).
; CHECK-NEXT: f - 'F' (Single-Precision Floating-Point).
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index b2e2450b6771e..f7380f9e52bac 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -414,6 +414,9 @@
.attribute arch, "rv32i_zvfbfwma1p0"
# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
+.attribute arch, "rv32i_zvfofp8min0p21"
+# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p21_zvl32b1p0"
+
.attribute arch, "rv32ia_zacas1p0"
# CHECK: attribute 5, "rv32i2p1_a2p1_zaamo1p0_zacas1p0_zalrsc1p0"
diff --git a/llvm/test/MC/RISCV/rvv/zvfbfmin.s b/llvm/test/MC/RISCV/rvv/zvfbfmin.s
index c5f05c6be0df9..8a497f0c055e9 100644
--- a/llvm/test/MC/RISCV/rvv/zvfbfmin.s
+++ b/llvm/test/MC/RISCV/rvv/zvfbfmin.s
@@ -19,24 +19,24 @@
# CHECK-INST: vfncvtbf16.f.f.w v8, v4, v0.t
# CHECK-ENCODING: [0x57,0x94,0x4e,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts) or 'Zvfofp8min' (Vector OFP8 Converts){{$}}
# CHECK-UNKNOWN: 484e9457 <unknown>
vfncvtbf16.f.f.w v8, v4, v0.t
# CHECK-INST: vfncvtbf16.f.f.w v8, v4
# CHECK-ENCODING: [0x57,0x94,0x4e,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts) or 'Zvfofp8min' (Vector OFP8 Converts){{$}}
# CHECK-UNKNOWN: 4a4e9457 <unknown>
vfncvtbf16.f.f.w v8, v4
# CHECK-INST: vfwcvtbf16.f.f.v v8, v4, v0.t
# CHECK-ENCODING: [0x57,0x94,0x46,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts) or 'Zvfofp8min' (Vector OFP8 Converts){{$}}
# CHECK-UNKNOWN: 48469457 <unknown>
vfwcvtbf16.f.f.v v8, v4, v0.t
# CHECK-INST: vfwcvtbf16.f.f.v v8, v4
# CHECK-ENCODING: [0x57,0x94,0x46,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}}
+# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts) or 'Zvfofp8min' (Vector OFP8 Converts){{$}}
# CHECK-UNKNOWN: 4a469457 <unknown>
vfwcvtbf16.f.f.v v8, v4
diff --git a/llvm/test/MC/RISCV/rvv/zvfofp8min.s b/llvm/test/MC/RISCV/rvv/zvfofp8min.s
new file mode 100644
index 0000000000000..5ac24dfc100e5
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/zvfofp8min.s
@@ -0,0 +1,36 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding -mattr=+experimental-zvfofp8min %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding -mattr=+v,+f %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+experimental-zvfofp8min %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zvfofp8min - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+experimental-zvfofp8min %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+experimental-zvfofp8min %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding -mattr=+v,+f %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+experimental-zvfofp8min %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-zvfofp8min - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+experimental-zvfofp8min %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# CHECK-INST: vfncvtbf16.sat.f.f.w v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x4f,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvfofp8min' (Vector OFP8 Converts){{$}}
+# CHECK-UNKNOWN: 484f9457 <unknown>
+vfncvtbf16.sat.f.f.w v8, v4, v0.t
+
+# CHECK-INST: vfncvt.f.f.q v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x4c,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvfofp8min' (Vector OFP8 Converts){{$}}
+# CHECK-UNKNOWN: 484c9457 <unknown>
+vfncvt.f.f.q v8, v4, v0.t
+
+# CHECK-INST: vfncvt.sat.f.f.q v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x4d,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvfofp8min' (Vector OFP8 Converts){{$}}
+# CHECK-UNKNOWN: 484d9457 <unknown>
+vfncvt.sat.f.f.q v8, v4, v0.t
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index cb4fbcae2f4da..e678ff4749b41 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1187,6 +1187,7 @@ Experimental extensions
zalasr 0.1
zvbc32e 0.7
zvfbfa 0.1
+ zvfofp8min 0.21
zvkgs 0.7
zvqdotq 0.0
svukte 0.3
|
|
Kindly ping. |
lenary
approved these changes
Sep 18, 2025
topperc
approved these changes
Sep 18, 2025
This patch adds MC support for Zvfofp8min https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfofp8min.adoc.
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/163/builds/26759 Here is the relevant piece of the build log for the reference |
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Sep 27, 2025
This patch adds MC support for Zvfofp8min https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfofp8min.adoc.
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This patch adds MC support for Zvfofp8min
https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfofp8min.adoc.